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 HD74HC640, HD74HC643
Octal Bus Transceivers (with 3-state outputs)
REJ03D0637-0200 (Previous ADE-205-517) Rev.2.00 Mar 30, 2006
Description
Each device has an active enable G and a direction control input, DIR. When DIR is high, data flows from the A inputs to the B outputs. When DIR is low, data flows from the B inputs to the A outputs. The HD74HC640 transfers inverted data from one bus to other and the HD74HC643 transfers inverted data from the A bus to the B bus and true data from the B bus to the A bus.
Features
* High Speed Operation: tpd = 12 ns typ (CL = 50 pF) * High Output Current: Fanout of 15 LSTTL Loads * Wide Operating Voltage: VCC = 2 to 6 V * Low Input Current: 1 A max * Low Quiescent Supply Current: ICC (static) = 4 A max (Ta = 25C) * Ordering Information
Part Name HD74HC640P HD74HC640FPEL HD74HC640RPEL HD74HC643RPEL Package Type DILP-20 pin SOP-20 pin (JEITA) SOP-20 pin (JEDEC) Package Code (Previous Code) PRDP0020AC-B (DP-20NEV) PRSP0020DD-B (FP-20DAV) PRSP0020DC-A (FP-20DBV) Package Abbreviation P FP RP -- EL (2,000 pcs/reel) EL (1,000 pcs/reel) Taping Abbreviation (Quantity)
Note: Please consult the sales office for the above package availability.
Function Table
Control Inputs G L L H H: L: X: high level low level irrelevant DIR L H X HD74HC640 B data to A bus A data to B bus Isolation Operation HD74HC643 B data to A bus A data to B bus Isolation
Rev.2.00 Mar 30, 2006 page 1 of 10
HD74HC640, HD74HC643
Pin Arrangement
HD74HC640
DIR A1 A2 A3 A4 A5 A6 A7 A8
1 2 3 4 5 6 7 8 9
20 VCC 19 Enable G 18 B1 17 B2 16 B3 15 B4 14 B5 13 B6 12 B7 11 B8
GND 10
(Top View)
HD74HC643
DIR A1 A2 A3 A4 A5 A6 A7 A8
1 2 3 4 5 6 7 8 9
20 VCC 19 Enable G 18 B1 17 B2 16 B3 15 B4 14 B5 13 B6 12 B7 11 B8
GND 10
(Top View)
Rev.2.00 Mar 30, 2006 page 2 of 10
HD74HC640, HD74HC643
Logic Diagram
HD74HC640
G DIR
VCC A B
VCC
To 7 Other Inverters
To 7 Other Inverters
HD74HC643
G DIR
VCC A B
VCC
To 7 Other Inverters
To 7 Other Inverters
Rev.2.00 Mar 30, 2006 page 3 of 10
HD74HC640, HD74HC643
Absolute Maximum Ratings
Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Symbol VCC VIN, VOUT IIK, IOK IO ICC or IGND PT Ratings -0.5 to 7.0 -0.5 to VCC +0.5 20 35 75 500 Unit V V mA mA mA mW
Storage temperature Tstg -65 to +150 C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time.
Recommended Operating Conditions
Item Supply voltage Input / Output voltage Operating temperature Input rise / fall time Note:
*1
Symbol VCC VIN, VOUT Ta tr , tf
Ratings 2 to 6 0 to VCC -40 to 85 0 to 1000 0 to 500
Unit V V C ns
Conditions
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
0 to 400 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics.
Electrical Characteristics
Item Input voltage Symbol VCC (V) VIH 2.0 4.5 6.0 2.0 4.5 6.0 Output voltage VOH 2.0 4.5 6.0 4.5 VOL 6.0 2.0 4.5 6.0 4.5 6.0 Off-state output current Input current Quiescent supply current IOZ Iin ICC 6.0 6.0 6.0 Min 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.18 5.68 -- -- -- -- -- -- -- -- Ta = 25C Typ Max -- -- -- -- -- -- 2.0 4.5 6.0 -- -- 0.0 0.0 0.0 -- -- -- -- -- -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.26 0.26 0.5 0.1 4.0 Ta = -40 to+85C Unit Min Max 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.13 5.63 -- -- -- -- -- -- -- -- -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.33 0.33 5.0 1.0 40 IOL = 6 mA IOL = 7.8 mA A Vin = VIH or VIL, Vout = VCC or GND A Vin = VCC or GND A Vin = VCC or GND, Iout = 0 A V V Vin = VIH or VIL IOH = -20 A V Test Conditions
VIL
V
IOH = -6 mA IOH = -7.8 mA Vin = VIH or VIL IOL = 20 A
Rev.2.00 Mar 30, 2006 page 4 of 10
HD74HC640, HD74HC643
Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = 25C Item Propagation delay time Symbol VCC (V) tPHL 2.0 4.5 6.0 tPLH 2.0 4.5 6.0 2.0 4.5 6.0 tZH 2.0 4.5 6.0 2.0 4.5 6.0 tHZ 2.0 4.5 6.0 2.0 4.5 6.0 -- Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ -- 12 -- -- 12 -- -- 15 -- -- 15 -- -- 17 -- -- 17 -- -- 4 -- 5 Max 90 18 15 90 18 15 230 46 39 230 46 39 215 43 37 215 43 37 60 12 10 10 Ta = -40 to +85C Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 115 23 20 115 23 20 290 58 49 290 58 49 270 54 46 270 54 46 75 15 13 10 pF ns ns ns Unit ns Test Conditions
Output enable time
tZL
ns
Output disable time
tLZ
ns
Output rise/fall time Input capacitance
tTLH tTHL Cin
ns
Test Circuit
HD74HC640
VCC VCC
G
See Function Table
Input Pulse Generator Zout = 50 Input Pulse Generator Zout = 50
Output A1 B1 CL = 50 pF DIR TEST t PLH / t PHL t ZH/ t HZ t ZL / t LZ S2 OPEN GND VCC S1 1 k S2 OPEN GND VCC
Notes : 1. CL includes probe and jig capacitance. 2. A2-B2, A3-B3, A4-B4, A5-B5, A6-B6, A7-B7, A8-B8 are identical to above load circuit. 3. S1 is a input / output swich.
Rev.2.00 Mar 30, 2006 page 5 of 10
HD74HC640, HD74HC643 HD74HC643
VCC VCC
G
See Function Table
Input Pulse Generator Zout = 50 Input Pulse Generator Zout = 50
Output A1 B1 CL = 50 pF DIR TEST t PLH / t PHL t ZH/ t HZ t ZL / t LZ S2 OPEN GND VCC S1 1 k S2 OPEN GND VCC
Notes : 1. CL includes probe and jig capacitance. 2. A2-B2, A3-B3, A4-B4, A5-B5, A6-B6, A7-B7, A8-B8 are identical to above load circuit. 3. S1 is a input / output swich.
Rev.2.00 Mar 30, 2006 page 6 of 10
HD74HC640, HD74HC643
Waveforms
HD74HC640
* Waveform - 1
tr 90 % 50 % t PHL 90 % 90 % 50 %
tf VCC 10 % t PLH 90 % 50 % 10 % t THL 50 % 10 % t TLH 0V
Input A 10 %
VOH VOL
Output B
* Waveform - 2
90 %
tf
tr 90 % 50 % 10 % t LZ VCC 0V VOH
Input G
50 % 10 % t ZL
Waveform - A t ZH Waveform - B
50 % t HZ
10 %
VOL VOH VOL
50 %
90 %
Notes : 1. Input waveform : PRR 1 MHz, duty cycle 50%, tr 6 ns, tf 6 ns 2. Waveform - A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform - B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The output are measured one at a time with one transition per measurement.
Rev.2.00 Mar 30, 2006 page 7 of 10
HD74HC640, HD74HC643 HD74HC643
* Waveform - 1
tr 90 % 50 % 10 % t PLH 90 % 90 % 50 %
tf VCC 10 % t PHL 90 % 50 % 10 % t THL 0V
Input B
VOH VOL
Output A
50 % 10 % t TLH
* Waveform - 2
tf 90 % 50 % 10 % t ZL 10 % t LZ VOH Waveform - A t ZH Waveform - B 50 % t HZ 90 % 10 % VOL VOH VOL Notes : 1. Input waveform : PRR 1 MHz, duty cycle 50%, tr 6 ns, tf 6 ns 2. Waveform - A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform - B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The output are measured one at a time with one transition per measurement. tr 90 % 50 % VCC 0V
Input G
50 %
Rev.2.00 Mar 30, 2006 page 8 of 10
HD74HC640, HD74HC643
Package Dimensions
JEITA Package Code P-DIP20-6.3x24.5-2.54 RENESAS Code PRDP0020AC-B Previous Code DP-20NEV MASS[Typ.] 1.26g
D
20
11
1 0.89 b3
10
Z
A1
A
E
Reference Symbol
Dimension in Millimeters
Min
e
bp
e1
c
( Ni/Pd/Au plating )
e1 D E A A1 bp b3 c e Z L
Nom Max 7.62 24.50 25.40 6.30 7.00 5.08
L
0.51 0.40 0.48 0.56 1.30 0.19 0.25 0.31 0 15 2.29 2.54 2.79 1.27 2.54
JEITA Package Code P-SOP20-5.5x12.6-1.27
RENESAS Code PRSP0020DD-B
Previous Code FP-20DAV
MASS[Typ.] 0.31g
*1
D 11
F
20
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
*2
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
10 bp x M L1
Reference Symbol
c
Dimension in Millimeters
y
A1
L
Detail F
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
Min Nom Max 12.60 13.0 5.50 0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 0.20 0.25 0 8 7.50 7.80 8.00 1.27 0.12 0.15 0.80 0.50 0.70 0.90 1.15
Rev.2.00 Mar 30, 2006 page 9 of 10
A
HD74HC640, HD74HC643
JEITA Package Code P-SOP20-7.5x12.8-1.27 RENESAS Code PRSP0020DC-A Previous Code FP-20DBV MASS[Typ.] 0.52g
*1
D
F 11
20
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" @ DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT @ INCLUDE TRIM OFFSET.
bp
HE E
*2
Index mark
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
c
Reference Symbol
Dimension in Millimeters
10 bp x M L1
A1
y
L
Detail F
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
Min Nom Max 12.80 13.2 7.50 0.10 0.20 0.30 2.65 0.34 0.40 0.46 0.20 0.25 0.30 0 8 10.00 10.40 10.65 1.27 0.12 0.15 0.935 0.40 0.70 1.27 1.45
Rev.2.00 Mar 30, 2006 page 10 of 10
A
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
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